The present invention relates generally to layered structures, and more particularly to layered structures produced using printing.
U.S. Patent Application Publication No. 2003/0186453 describes nanocalorimeter arrays with thermal isolation regions on a substrate. A thermal isolation layer can include a plastic material in thin foil form ranging from less than 15 μm to approximately 25 μm in thickness, possibly as thin as 2 μm and as thick as 500 μm. Thermal equilibrium regions contain resistive thermometers, drop merging electrodes, and insulating layers deposited using standard fabrication techniques, such as lithographic patterning of thin films, microelectronic fabrication techniques (e.g. including sputtering, chemical etching, evaporation), and printed circuit board fabrication techniques. If amorphous silicon thermometer material is deposited, such as at temperatures in the range of 170-250° C., a substrate polymer film should have a high softening temperature. Deposition of vanadium oxide thermometer material can be done at a substantially lower temperature, allowing a substrate polymer with a lower softening point.
U.S. Patent Application Publication No. 2003/0134516 describes fabrication of large-area pixel arrays for displays and sensors. A droplet source ejects droplets of a masking material on a thin film or substrate surface to mask an element of an array of electronic devices. The thin-film or substrate is etched, and then the masking material is removed.
U.S. Patent Application Publication No. 2005/0136358 describes liftoff operations in which a liftoff pattern is printed. The liftoff operations can be used to produce large arrays of thin film transistors (TFTs), such as for addressing individual pixels in a display.
It would be advantageous to have improved techniques for layered structures on support structures.